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interfacing otg243 usb host/function/otg controller to MCF5272 coldfire processor reference design transdimension inc. 2 venture irvine, ca 92618 www.transdimension.com phone: (949) 727-2020 fax: (949) 727-3232 sales@transdimension.com techsupport@transdimension.com tdi document number: mu2017 rev. 1.00: september, 2002
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor the device and its documentation are provided ?as is?. transdimension hereby disclaims all warranties, express, statutory and implied, applicable to the software and its documentation and any related products, including, but not limite d to, any warranty of merchantability, non- infringement or fitness for a particular purpose. transdimension assumes no liability for any act or omission of the licensee. in no event sha ll transdimension be liable for direct, special, indirect, incidental, punitive, exem plary or consequential damages, including, without limitation, loss of profits or revenue, loss of products, data or any associated equipment, cost of capital, cost of substituted equipment or parts, facilities or services, down-time or labor costs, even if transdimension has been advised of the possibility thereof. the device and any related products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applicatio ns. any such use and subsequent liabilities that may arise from such use are totally the res ponsibilities of the licensee. ? 2002, transdimension inc., all rights reserved. all product names are trademarks or register ed trademarks of their respective owners.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor revision history version number release date notes 1.00 september, 2002 first release note: this document is subject to change without notice
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor contents 1. introduction................................................................................................................ ..........1 1.1 system overview .....................................................................................................1 1.2 references................................................................................................................2 1.3 notation................................................................................................................... .2 1.4 software ................................................................................................................... 2 2. bus interface ............................................................................................................... .........3 2.1 recommendations....................................................................................................3 2.2 required procedure..................................................................................................3 2.3 hardware design .....................................................................................................3 operating mode: / exvbo and test ....................................................................3 bus control: /cs , /rd , and /wr .............................................................................4 address bus: a 8 :a 2 ..................................................................................................4 data bus: d 31 :d 0 .....................................................................................................4 hardware reset: /reset .......................................................................................4 interrupt: int ..........................................................................................................4 crystal oscillator and pll: osc 1 and osc 2 .........................................................5 dma: drq 1 , dack 1 , eot 1 , drq 2 , dack 2 , and eot 2 ........................................5 remote wakeup: wakeup ....................................................................................5 external pull-up: rpu ............................................................................................5 overcurrent: /oc ....................................................................................................6 power on: /po ........................................................................................................6 2.4 software configuration............................................................................................6 bus cycle timing .....................................................................................................6 MCF5272 chip select programming ......................................................................7 software controlled otg243 reset ......................................................................10 software controlled remote wakeup ....................................................................11 interrupt: MCF5272 configuration.......................................................................11 interrupt: otg243 configuration .........................................................................12 usb system initialization ......................................................................................12 2.5 otg243 access .....................................................................................................12 otg243 memory map...........................................................................................12 otg243 register access .......................................................................................14 otg243 on-chip memory access ........................................................................14 3. usb port circuits ........................................................................................................... ...15 3.1 otg243 port 2 and port 3 .....................................................................................15 usb signal lines ...................................................................................................15 usb host power distribution................................................................................16 3.2 otg243 port 1.......................................................................................................16 usb signals ...........................................................................................................16 vbus circuit...........................................................................................................16 software considerations........................................................................................16 4. power and ground ............................................................................................................ .16 5. reference design schematics............................................................................................17 6. otg243 module for ucevolution development platform...............................................17
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 7. technical support ........................................................................................................... ...19
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 1 1. introduction 1.1 system overview transdimension?s otg243 is a low cost, hi gh-performance, easily programmable device designed specifically for embedded usb host , usb function , and usb on-the-go (otg) dual role device (drd) applications. it can be configured to operate as: ? a standard usb otg drd contro ller (port 1) and a standard usb 2-port host controller (port 2 and port 3). ? a standard usb 2-port host cont roller (port 2 and port 3), and a standard usb function controller (port 1). ? a standard usb 3-port host controlle r (port 1, port 2 and port 3). the chip is designed for the embedded usb applications, especially mobile and post-pc products, including cell phones, palm platforms, pe rsonal digital assistan ts, set top boxes, home gateway systems, and internet appliances. peer -to-peer communication is made simple with the otg243 as usb connectivity may be achieved wit hout the intervention of a personal computer. the block diagram for the otg243 is shown below. figure 1: otg243 block diagram /reset /cs /wr /rd drq 1 dack 1 eot 1 drq 0 dack 0 eot 0 a 8 :a 2 d 31 :d 0 int wakeup /exvbo test pll osc 2 osc 1 48 mhz 12 mhz memory blocks otg trans- ceiver dm 3 dp 3 host sie & root hub p interface usb host controller registers system configuration & control registers usb function controller registers usb host control logic function sie usb trans- ceiver usb trans- ceiver dm 2 dp 2 dm 1 dp 1 /po /oc charge pump & vbus control circuit hnp/ srp logic id rpu test control cex 1 cex 2 vfb vbus vbp psh usb function control logic h/f psf psh psc
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 2 1 nc 21 v dd 41 d 26 61 v dd 81 vbus 2 d 0 22 v dd 42 d 27 62 v dd 82 vfb 3 d 1 23 v ss 43 v ss 63 wakeup 83 /oc 4 d 2 24 test 44 v dd 64 int 84 /po 5 v dd 25 nc 45 dp 2 65 /reset 85 id 6 v dd 26 /cs 46 dm 2 66 vbp 86 v ss 7 d 3 27 /wr 47 dp 3 67 a 2 87 v dd 8 d 4 28 /rd 48 dm 3 68 a 3 88 v dd 9 d 5 29 d 16 49 nc 69 a 4 89 /exvbo 10 d 6 30 d 17 50 nc 70 a 5 90 drq 1 11 d 7 31 d 18 51 nc 71 a 6 91 drq 0 12 v ss 32 d 19 52 rpu 72 a 7 92 dack 1 13 d 8 33 d 20 53 dp 1 73 a 8 93 dack 0 14 d 9 34 d 21 54 dm 1 74 nc 94 eot 1 15 d 10 35 d 22 55 v ss 75 nc 95 eot 0 16 d 11 36 d 23 56 d 28 76 av dd 96 v ss 17 d 12 37 v dd 57 d 29 77 av ss 97 av ss 18 d 13 38 v ss 58 d 30 78 cex 1 98 osc 1 19 d 14 39 d 24 59 d 31 79 v dd 99 osc 2 20 d 15 40 d 25 60 v ss 80 cex 2 100 av dd figure 2 : otg243 pin assignment (lqfp) 1.2 references general instructions on otg243 interfacing are gi ven in chapters 6 and 7 of the otg243 data sheet (tdi document number: mu2001). this refe rence design describes a specific interfacing design of otg243 with motorola MCF5272 coldfire ? . it is assumed that the user ha s knowledge on general principles of microprocesso r interfacing, as well as some understanding on the motorola MCF5272 and the otg243. reading chapter 7 of usb specification 2.0 is recommended. 1.3 notation for clarity, all otg243 signal names in the following are in italic bold : e.g., a 4 and vbus , and active low signals are writ ten with leading ?/?: e.g., /wr . MCF5272 names are in plain bold : e.g., a4 and ncs0 , and active low signals are written with leading ?n?: e.g, cs0 is written as ncs0 . 1.4 software transdimension, together with soft connex inc, its wholly owned s ubsidiary, offer total solutions including controller chips, re ference designs, development kits , firmware for microprocessor interfacing, hcd (host controlle r driver), hnp (host negotiati on protocol), srp (session request protocol) as well as usb host and function stacks running unde r most real time operating systems.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 3 2. bus interface 2.1 recommendations for the MCF5272, we recommend that: ? the otg243 is interfaced dire ctly to MCF5272?s system bus. ? the otg243 operates in 16-bit mode (pin /exvbo pulled-down). this reference design has been tested in 16-bit mode, but should work just as well in 32-bit mode. ? the otg243 is accessed through the MCF5272 ch ip-select as memory-mapped peripheral. any of the chip-select signals ncs[5:2] can be programmed for an address location, with masking capabilities, port size, burst capabi lity indication, and wait-state generation. ncs2 is used for this reference design. ? the chosen chip-select is programmed to 16-bit access with a bus cycle compatible to that of the otg243?s. the above recommendations are assumed throughout this document. alternative interfacing schemes, such as 32-bit access to th e otg243, can function just as well. 2.2 required procedure MCF5272 operates under big endian mode, but ot g243 operates under the li ttle endian mode. software is required to perf orm byte swapping for the data. 2.3 hardware design this sub-section discusses hardware aspects of interfacing the otg243 to the MCF5272. software considerations ar e presented in section 2.3. the following signals of the otg243 are involved in the bus interfacing. for simplicity and clarity, buffers are not inserted between the mc f5272 and the otg243. one should use his/her own judgment on this issue ba sed on a specific application. operating mode: / exvbo and test /exvbo should be pulled down for 16-bit operation, and the test pin must be grounded.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 4 bus control: / cs , / rd , and / wr in this reference design, the ot g243 is accessed through MCF5272?s ncs2 (base memory address 40000000). thus otg243 chip select /cs , read strobe /rd , and write strobe /wr should be tied to ncs2 , noe/rd , and r/nw of the MCF5272, respectively. address bus: a 8 :a 2 the otg243 address bus a 8 :a 2 is connected to a8:a2 of the MCF5272. data bus: d 31 :d 0 the lower 16-bit data bus of the otg243 d 15 :d 0 should be connected to d 31 :d 16 of the MCF5272. this is due to MCF5272 data bus d 15 :d 0 becoming gpio port c when configured as 16-bit external data bus. the uppe r 16-bit data bus of the otg243 d 31 :d 16 should be pull-down with 15k resistors. hardware reset: /reset for many applications, the otg243 /reset can be tied to MCF5272?s system reset ( nrsti or nrsto ). however, it is recommended that a mc f5272 gpio pin be allocated as the otg243 hardware reset for flexibility of user software. in this reference design, pc12 (gpio port c bit 12) of the MCF5272 is assigned to the otg243?s /reset , and its selection depends on the appl ication. to improve reliability, a pull- up resistor is desired. an rc filter circuit is highly recommended to eliminate unexpected noise triggered reset. interrupt: int the interrupt signal int generated by the otg243 must be tied to one of the six nint n pins of the MCF5272. in this reference design, MCF5272 pin nint2 is employed, and its selection again depends on the application. note that the active level (activ e high or active low) and the out put type (totem-pole or wired or) of the otg243 int pin are programmable. for this reference design, the otg243 int pin is to be programmed to active low, totem-pol e operation. a pull-up resistor is recommended.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 5 crystal oscillator and pll: osc 1 and osc 2 in the reference design, a 6 mhz parallel resonance quartz crystal is connected across osc 1 and osc 2 . the following circuit is recommended. figure 3: otg243 crystal oscillator circuit to meet the usb frequency accuracy and stability requirements, the crystal should have an accuracy and stability better than 200 ppm. for a 6 mhz resonance quartz crystal, the recommended esr value should be less than 100 ? . dma: drq 1 , dack 1 , eot 1 , drq 2 , dack 2 , and eot 2 in this reference design, dma is not tested and not supported. when these signals are not used, proper connec tions should be made by pulling up or down according to the application. the logic levels of drq 1 and drq 2 at the time of hardware reset determine the frequency of the oscillation imposed on the osc 1 and/or osc 2 pins. in this referenc e design, a 6 mhz crystal is employed. therefore the drq 1 and drq 2 should be tied with pull-dow n resistors smaller than 10k ? . since dack 1 , dack 2 , eot 1 , and eot 2 signals are all configured as inputs and active low signals right after reset, they should be pulled-up by resistors. note: even though the MCF5272 has a one-channe l dma controller in ternal to MCF5272, which supports memory-to-memory dma transfers that can be used for block data moves, it does not require any external signals for dma tr ansfer. it uses normal memory access signals for dma transfer. remote wakeup: wakeup this pin is only meaningful if po rt 1 of the otg243 is assuming the role of a usb function. in this reference design, a MCF5272 gpio pin ( pc13 ) is assigned to it. since wakeup is active high, a pull-down resistor is recommended. external pull-up: rpu if the internal pull-up resistor does not satisfy the usb 1.5k ? pull-up tolerance, an external 1.5k ? +/- 1% can be connected from rpu signal to dp 1 signal. 100 osc 2 6.8 pf otg243 osc 1 6.8 pf 6.000 mhz
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 6 this pin should be left floating if external 1.5k ? pull-up resistor is not used. overcurrent: /oc it is recommended to add an extern al pull-up for overcurrent signal. power on: /po this ganged power-on signal is an output, so it is ok to leave it floating if not used. however, do not use pull-up resistor if this signal is used in a low power application. if otg243 is put into power-save mode with /po signal asserted, there will be unnecessary current leakage through this pull-up resistor. 2.4 software configuration bus cycle timing bus cycle timing parameters for the otg243 read /write operation are listed below. the otg243 register read and register write cycles ar e illustrated in figures 5 and 6, respectively. symbol parameter min max unit t rpw /rd pulse width 55 ns t wpw /wr pulse width 55 ns t acr access cycle recovery time 25 ns t asl address setup time before /rd or /wr goes low 0 ns t ahh address hold time after /rd or /wr high 0 ns t dsw data setup time before /wr high 45 ns t dvr data valid time after /rd low 55 ns t dhr data hold time after /rd high 3 ns t dhw data hold time after /wr high 0 ns t crwl /cs low to /rd or /wr low 0 ns t rwch /rd or /wr high to /cs high 0 ns figure 4: otg243 bus cycle timing parameters
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 7 figure 5: otg243 register read cycle figure 6: otg243 register write cycle MCF5272 chip select programming based on the otg243 register re ad/write cycle specif ication, the chip select base registers (csbr2) and the chip select option registers (csor2) for ncs2 may be programmed according to the following: c s a 8 :a 2 d 15 :d 0 valid address valid data t wpw t acr t dsw t asl wr t ahh t crwl t dhw t rwch cs a 8 :a 2 valid address d 15 :d 0 valid data t rpw t acr t dvr t asl rd t ahh t crwl t dhr t rwch
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 8 csbr2 addr : 0x050 default value after reset : 0x0000_2300 field bits function settings meaning default ba 31:12 base address. 4000_0 starting address 0000_2 ebi 11:10 external bus in terface modes. 00 16/13-bit sram/rom 00 bw 9:8 bus width. 10 word (16 bits) 11 super 7 supervisor mode. 0 user or supervisor mode 0 tt 6:5 transfer type. 00 don?t care, since ctm is not set. 00 tm 4:2 transfer modifier. 000 don?t care, since ctm is not set. 000 ctm 1 compare tm. 0 tt & tm register bits do not affect address match. 0 enable 0 enable 1 cs2 enabled 0
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 9 csor2 addr : 0x054 default value after reset : 0xffff_f078 field bits function settings meaning default bam 31:12 address mask ffff_f compare address bits ffff_f aset 11 address setup enable 1 delay assertion of chip select for one clk cycle after address is asserted. during write transfers, both chip select and r/nw are delayed by 1 clock cycle. 0 wrah 10 controls the address, data and attribute hold time after the termination, internal or external with /ta, of a write cycle that hits in the chip select address space. 1 hold address, data, and attribute signals an extra cycle after ncs2 and r/nw negate on writes 0 rdah 9 controls the address and attribute hold time after the termination, internal or external with /ta, of a read cycle that hits in the chip select address space. 1 hold address and attribute signals an extra cycle after chip select negate on reads. 0 extburst 8 enable extended burst. - vailid only for ncs7 . 0 - 7 reserved, should be cleared. 0 ws 6-2 wait state generator 00011 3 wait states 11110 rw 1 rw and mrw determine whether the selected memory region is read only or write only. 0 don?t care since mrw is cleared. 0 mrw 0 mrw must be set for value of rw be taken into consideration. 0 memory covered by chip select is read/write 0 pbcnt addr : 0x088 default value after reset : 0x0000_0000 field bits function settings meaning default pbcnt5 11:10 port b control regitster. pb5/nta select 00 select pb5 00 figure 7: MCF5272 register csbr2, csor 2, & pbcnt settings to generate ncs2
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 10 figure 8: MCF5272 bus read cycle gene rated using parameters of figure 7 figure 9: MCF5272 bus write cycle gene rated using parameters of figure 7 the memory map of ncs2 is determined by 2 parameters. the content of ba field in csbr2 register determines the starting address of the ncs2 . the content of bam field in csor2 register determines the memory block size of ncs2 . in this design the starting address is set to 0x40000000, and the block size is set 4k byte. the wait states are controlled by the combinati on of aset, wrah, rdah, and ws fields in csor2 register. in this design, aset, wrah, and rdah are set and ws is set to 3 wait states. also, the transfer acknowledge ( nta) signal is not utilized but this signal is assigned as gpio port pb5 in this reference design. note that these settings are ba sed on the assumption that the mc f5272 is running at an external 48 mhz oscillator. they are set for the mcf 5272 to generate near- optimal access cycles satisfying the otg243 specification. it is advised that one starts wi th a much looser (slower) set of timing parameters, such as 1fh, applied to the ws field of this csor2 register, and then have them fine-tuned towards optimal performance. software controlled otg243 reset cs 104 ns > 62.4 ns wr a 8 :a 2 valid address 20.8 ns > 20.8 ns cs 104 ns > 104 ns rd a 8 :a 2 valid address 20.8 ns > 20.8 ns
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 11 it is assumed that pc12 of the MCF5272 is employed to support software controlled /reset for the otg243. the MCF5272 gpio registers shou ld be initialized according to figure 12. register address register full name bit 12 meaning default pcddr 0x0094 port c data direction register 1 output 0 pcdat 0x0096 port c data register 1 no reset undefined figure 12: MCF5272 gpio register sett ings to support software generated /reset to issue an otg243 reset through software, one must step 1: write to gpio register pcdat with a bit pattern such that bit 12 = 0. this asserts the active low otg243 pin /reset . step 2: wait for at least 40 s. step 3: write to gpio register pcdat with a bit pattern such that bit 27 = 1. this de-asserts the active low otg243 pin /reset . software controlled remote wakeup it is assumed that pc13 of the MCF5272 is employed to support software controlled /wakeup for the otg243 function operation. the MCF5272 gpio registers shou ld be initialized according to figure 13. register address register full name bit 13 meaning default pcddr 0x0094 port c data direction register 1 output 0 pcdat 0x0096 port c data register 0 no wakeup undefined figure 13: MCF5272 gpio register sett ings to support software generated wakeup to issue a remote wakeup to the otg243 through software, one must step 1: write to gpio register pcdat with a bit pattern such that bit 13 = 1. this asserts the active high otg243 wakeup . step 2: wait for at least 1 s. step 3: write to gpio register pcdat with a bit pattern such that bit 13 = 0. this de-asserts the active high otg243 wakeup . interrupt: MCF5272 configuration in the following discussion, it is assumed that nint2 of the MCF5272 is c onnected to otg243?s int pin, which has been programmed to be active low with totem-pole output. the MCF5272?s interrupt control register s should be initialized as follows:
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 12 register address register full name bits bit values meaning default icr1 0x020 interrupt control register 1 27:24 1011 interrupt priority level 0000 pitr 0x034 programmable interrupt transition register 30 0 negative edge triggered 0 figure 14: MCF5272 gpio register se ttings to support otg243 interrupt please note that the interrupt ge nerated by the otg243 is level sens itive. caution must be taken when it is interfaced with an in terrupt controller, such as the one in the MCF5272, that supports only edge-sensitive interrupt sources. interrupt: otg243 configuration the software must configure the otg243 before the MCF5272 enables the interrupt originated from it. the following steps must be carried out: step 1: configure the otg243 int pin to be active low. this requires bit 16 of the otg243 hardwaremode register (000h) be set to 0, which is the default. step 2: configure the otg243 int pin to be totem-pole output. this requires bit 21 of the ioconfiguration2 register (04ch) to be se t to 1 by user software. note that the int pin defaults to wired or output, which should also work if a pull-up resistor is present. step 3: enable interrupt sources on the otg243 si de, which involves four sets of registers as described in detail in secti on 7.4 of the otg243 data sheet. usb system initialization it should be emphasized that all MCF5272 regist er settings and the otg243 hardware system settings discussed above must be completed be fore the usb controller s within the otg243 are activated. 2.5 otg243 access otg243 memory map the otg243 control registers and internal me mory blocks are accessed through a two-level memory map as shown in figure 9. it should be emphasized that all regi sters and data accesses are in 32-bit double word (dword), even if the otg243 is placed on a 16-bit bus. in the latter case, a pair of 16-bit accesses (first for the leas t significant 16-bits, and the second for the most significant two bytes) must be issued successfully by the microprocessor for reading or writing a single dword. thus the least signifi cant two bits of the address bus (a 1 and a 0 ) are always treated as 00b.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 13 the MCF5272 communicates with the otg243 through the primary memory map (pmm), consisting of 128 dword registers. thus all ot g243 accesses to the otg243 are register reads or register writes. in other words, the micr oprocessor does not access the otg243?s internal memories. the etd memory (128 dwords) and the data memory (1k dwords) inside the otg243 are accessed through an address register named memo ryaccessstartaddress re gister (0a4h), and a data port register called piodataport register (02ch) using the standard two-stage access methodology. if the memoryaccesstype bit (bit 15 of the memoryaccessstartaddress register) is 0, the etd memory is accessed. othe rwise, the data memory is read from or written into. it must be emphasized that the address specified in the memoryaccessstarta ddress register is in dwords, not in bytes, relative to the beginning of the etd memory or the data memory, respectively. using burst read and burst writ e, the otg243 supports fast data movement between the microprocessor and on-chip memory.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 14 000h : etd 0 0000h 004h : etd 1 0008h : : etd 2 0010h 02ch piodataport : : : : : : 0a4h : : 1fch : etd f 0078h 0080h 7fffh data 8000h data 8001h : : : : data 83ffh 8400h ffffh figure 9: otg243 memory map otg243 register access in this reference design, the physical addre ss used by the MCF5272 to access otg243 address m in its pmp is 40000000h + m , where 000h m 1ffh. note that the le ast significant two bits of m are always treated as 00b. otg243 on-chip memory access the etd memory (128 dwords) and data me mory (1k dwords) can be accessed through a procedure called programmed i/o (pio), which is carried out as follows: step 1: write into memoryaccessstartaddress register an access word indicating (i) memory segment - either etd memory or data memory; (ii) access address - offset to the beginning of the memory segment indicated in (i ). note that the unit of this address is dwords, not bytes; and (iii) intended access di rection - read or write. formats of the access word for the etd memory and that for the data memory are given in figures 10 and 11, respectively. registers 512 bytes etd memory 128 dwords data memory 1k dwords reserved reserved reserved reserved bit 15 = 0 primary memory map (512 bytes) secondary memory map (64k dwords) bit 15 = 1 memaccessstartaddress register mcf527
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 15 bit description 8:0 address (relative to the beginning of the respective memory) in dwords. 14 access direction. 1 for write and 0 for read. 15 selection between etd memory (0) and data memory (1). 13:9, 31:16 reserved. should be filled with 0's . figure 10: etd memory access word bit description 11:0 address (relative to the beginning of the respective memory) in dwords. 14 access direction. 1 for write and 0 for read. 15 selection between etd memory (0) and data memory (1). 13:12, 31: 16 reserved. should be filled with 0's. figure 11: data memory access word step 2: wait until the pio cha nnel is ready by examining the pioready bit (bit 0) of the pioready register (044h). continue to st ep 3 only after the bit has become low. step 3: write into, or read from the piodataport register (02ch) for one dword, or a block of consecutive dwords. in the latter cas e, the accessing address is increased automatically. the access directi on (read/write) in this step should be cons istent with that specified in the access word. (if not, the a ccess direction indicated in the access word takes precedence.) 3. usb port circuits this section discusses circuits between the usb ports of the ot g243 and their connectors. note that these issues are generic a nd in fact independent to that of the MCF5272 interfacing. one should consult chapter 7 of the usb specificatio n 2.0, as well as chap ters 6 and 7 of the otg243 data sheet for details. 3.1 otg243 port 2 and port 3 these two ports can only serve as standard dow nstream host ports. thus they use usb type a receptacles. usb signal lines two 15 k ? pull-down resistors are required on the dp n and dm n (n = 2, 3) data lines to support detection of a device connec ting or disconnecting event. to satisfy the impedance matching requirement, a 33 ? resistor should be inserted between a usb data line ( dp n or dm n ) and its corresponding pin at the usb type a connector.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 16 if a port is not used, its dm n and dp n pins must be pulled down via 15 k ? resistors. they cannot be grounded directly or be left floating. usb host power distribution in this reference design, ti?s dual power-d istruibution switch t ps2042 is employed. when the current flowing through this device ex ceeds the current-limit threshold (0.9a) or a short is present, the /oc pin of the otg243 is asserted. as an alternative, a poly- switch resettable device (n anosmd100, specially made by raychem/tyco for usb app lications) can be used. a sufficiently large capacitor (more than 120 f) is applied to the vbus of each port, per usb specification. ferrite beads are inserted in the vbus and ground circuits for emi reduction. 3.2 otg243 port 1 this port can be configured as a standard usb host port, a standard usb function port, or an otg port. the details are given in section 6 of the otg243 data sh eet. in this reference design, port 1 serves as a port for a usb otg dual role device. usb signals the usb signal circuits for port 1 (dm1, dp1) are similar to that of port 2 and port 3, except that the two pull-down resistors are integrated with the otg transceiver circ uit. in addition, this reference design chooses the internal pull-up resist or when the otg243 assumes the role of a full speed usb function. vbus circuit in the reference design, the intern al charge pump is used as the vbus power source. as an a- device, it supplies the power of 5v of up to 12 ma. as a b- device, it is the power source for ?vbus pulsing?. a capacitor of 0.47 f must be connected between otg243 pins cex 1 and cex 2 . two 2.2 f capacitors and a 10 h inductor constitutes a low pass filter for the charge pump output. a 10 ? resistor and a 1 f capacitor serve as part of the voltage feedback. software considerations operating as a usb otg controller, the otg 243 implements the hnp/srp (host negotiation protocol and session request prot ocol), which configures port 1 circuit dynamically. for details, please contact transdimen sion technical support for details. 4. power and ground
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 17 the chip can be used with a si ngle dc power supply of 3.3v. v dd and av dd should be connected at only one point on a printed ci rcuit board. this also applies to v ss and av ss . all logic i/o pins are lvcttl compatible, and 5v tolerant. 5. reference design schematics the schematic drawing on page 14 is based on several assumptions made in the above discussion. it must be modified according to one?s application. 6. otg243 module for ucevolution development platform transdimension has developed an otg243 module (cxb243) that can be plugged into the sodimm bus of the ucevolution developmen t platform with ucdimm coldfire 5272 microcontroller module, allowi ng quick otg243 evaluation and user software development. contact tdi technical support for details.
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 18 c8 2200 pf r20 15k d6 cf_pc13 r9 15k usb-a j2 3 2 1 4 5 d+ d- +5v gnd shd cf_nint2 c10 33 uf r15 15k r2 100 cf_pc12 r23 15k 3.3v c1 0.47 uf a7 d14 c18 0.1 uf cf_ncs2 a6 c13 0.01 uf r17 39x2 r7 15k 3.3v 5v r28 4.7kx2 r18 15k a5 c4 2.2 uf c16 0.1 uf c17 0.1 uf c3 6.8 pf j1 mini-ab 3 2 1 5 4 6 d+ d- +5v gnd id shld r8 15k c21 0.1 uf r12 33x2 b l2 b l3 d4 r1 4.7kx4 r27 4.7kx8 l1 10 uh a3 d10 c14 150 uf r22 15k r24 15k d3 c20 1000 pf r11 15k a2 r26 39x2 c6 1.0 uf sc-otg243-a6.1-001 1.0 otg243:MCF5272 coldfire reference design a 11 monday, september 16, 2002 title size document number rev date: sheet of r16 15k b l5 a3.3v 3.3v u1 otg243_lqfp100 65 98 99 26 28 27 64 73 72 71 70 69 68 67 90 91 93 92 95 94 59 58 57 56 42 41 40 39 36 35 34 33 32 31 30 29 20 19 18 17 16 15 14 13 11 10 9 8 7 4 3 2 63 24 54 53 85 78 80 89 46 45 48 47 83 84 52 43 38 23 12 22 37 44 62 55 61 21 66 81 82 5 6 87 88 60 86 96 79 76 100 77 97 reset osc1 osc2 cs rd wr int a8 a7 a6 a5 a4 a3 a2 drq1 drq0 dack0 dack1 eot0 eot1 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 wakeup test dm1 dp1 id cex1 cex2 exvbo dm2 dp2 dm3 dp3 oc po rpu vss43 vss38 vss23 vss12 vdd22 vdd37 vdd44 vdd62 vss55 vdd61 vdd21 vbp vbus vfb vdd5 vdd6 vdd87 vdd88 vss60 vss86 vss96 vdd79 avdd76 avdd100 avss77 avss97 d15 r29 0 c9 0.01 uf cf_noe/rd d1 r19 15k transdimension inc. b l7 r3 10 cf_r/nw r6 4.7k c11 0.01 uf 3.3v b l4 a8 d5 c15 0.01 uf d9 r14 15k usb-a j3 3 2 1 4 5 d+ d- +5v gnd shd d13 c12 150 uf a3.3v r25 33x2 r5 33x2 d12 c7 22pf a4 c5 2.2 uf u2 tps2042d 3 4 8 5 7 6 1 2 en1 en2 oc1 oc2 out1 out2 gnd in b l6 d11 d8 cf_a[8:2] d2 r4 130 r13 15k y1 6 mhz r21 15k 5v d7 r10 15k c19 0.1 uf d0 c2 6.8 pf cf_d[31:16]
transdimension inc. interfacing otg243 to motorola MCF5272 coldfire processor 19 7. technical support technical questions should be addressed to: technical support transdimension inc. 2 venture irvine, ca 92618, usa +1 (949) 727-2020 x242 (phone) +1 (949) 727-3232 (fax) email: techsupport@transdimension.com for additional information, contact your transdimension sales representative or the following: internet: http://www.transdimension.com e-mail: sales@transdimension.com , techsupport@transdimension.com . headquarters: transdimension inc., 2 venture, irvine, ca 92618, usa. tel: +1(949) 727-2020, fax: +1(949) 727-3232 pete todd, vp of sales, e-mail: ptodd@transdimension.com america: transdimension inc., 815 west market st., suite 804, louisvile, ky 40202, usa. tel:+1(502)992-3226 larry hayden, e-mail: lhayden@transdimension.com japan: transdimension inc., oya bldg. 5, 3 chome-9-6, nishishin juku, shinjuku-ku, tokyo, japan. tel: +81(3) 5308-7525, fax: +81(3) 5308 7526 masanori sugane , e-mail: sugane@alto.ocn.ne.jp . asia (excluding japan): transdimension inc., 3 ubi ave 3, #05-01 crocodile house, singapore, 408857. tel: +65 6743 9179, fax +6 5 6741 4393 t. l. nge, e-mail: tlnge@transdimension.com europe: transdimension inc., 7 the orchard, hilton, derbyshire, uk, de65 5jf. tel: +44 1283 730045 , fax: +44 1283 730651 neil huntingdon , e-mail: nhuntingdon@transdimension.com worldwide reps.: see detailed listing for your area transdimension representative by viewing http://www.transdimension.com . _______________________________________________________________________________________________________________________________ ______ ? 2002, transdimension inc. all rights reserved printed in usa august, 2002 mu2017, rev. 1.00

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